1. Field of the Invention
The present invention relates to a semiconductor device mounted by wire bonding and to a method of producing the semiconductor device.
2. Description of the Related Art
Conventionally, semiconductor devices of a package configuration, such as the Small Outline Package (SOP), the Dual Inline Package (DIP), the Pin Grid Array (PGA), and the Quad Flat Package (QFP), which all accommodate a semiconductor chip in a package, have been known. Moreover, various semiconductor devices of a multi-chip package configuration, in which several semiconductor chips are accommodated in a single package, have been proposed in order to improve packaging density.
Examples of documents concerning semiconductor devices of the multi-chip package configuration include the following.
Document 1: Japanese Patent Application Laid-open Publication (JP-A) No. 2000-332194
Document 2: Japanese Patent Application Laid-open Publication (JP-A) No. 2001-7277
FIGS. 14A and 14B are schematic structural views of a conventional SOP semiconductor device, with FIG. 14A being a plan view and FIG. 14B being a longitudinal sectional view. FIGS. 15A and 15B are schematic structural views of another conventional SOP semiconductor device in which exterior pull-out lead positions are different from those of FIGS. 14A and 14B, with FIG. 15A being a plan view and FIG. 15B being a longitudinal sectional view.
In the semiconductor device of FIGS. 14A and 14B, a semiconductor chip 20A is mounted using a lead frame 10A. As shown in FIG. 14A, the lead frame 10A includes a die pad 11A for mounting a semiconductor chip, with the die pad 11A being substantially rectangular in plan view. A plurality of leads 12A are vertically disposed a predetermined distance away from upper and lower edges of the die pad 11A. Each lead 12A includes an inner lead portion disposed with a bonding pad 13A and an outer lead portion that is pulled out to the exterior.
The semiconductor chip 20A, which is rectangular when seen in plan view, is fixed on the die pad 11A. As seen in FIG. 14A, bonding pads 21A are disposed near upper and lower edges of an upper surface of the semiconductor chip 20A in correspondence to the positions at which the bonding pads 13A of the lead frame 10A are disposed. The bonding pads 21A of the semiconductor chip 20A are connected to the bonding pads 13A of the lead frame 10A by wires 14A. The semiconductor chip 20A and the wires 14A are resin-sealed with a resin member 15A.
Because the semiconductor device of FIGS. 15A and 15B is packaged using a lead frame 10B, in which the pull-out direction of the leads is different from that of the lead frame 10A of FIGS. 14A and 14B, a semiconductor chip 20B is used in which the positions at which the bonding pads are disposed are different from those of the semiconductor chip 20A of FIGS. 14A and 14B.
Namely, in the lead frame 10B of FIGS. 15A and 15B, plural leads 12B are, as shown in FIG. 15A, horizontally disposed at a predetermined distance away from left and right edges of a die pad 11B, which is rectangular in plan view. Each lead 12B includes an inner lead portion disposed with a bonding pad 13B and an outer lead portion that is horizontally drawn out.
Although the semiconductor chip 20B, which is rectangular in plan view and fixed on the die pad 11B, has a function that is identical to that of the semiconductor chip 20A of FIGS. 14A and 14B, it is newly created distinct from the semiconductor chip 20A of FIGS. 14A and 14B so that the bonding pads 21B are disposed near left and right edges of the upper surface in order to correspond to the positions at which the bonding pads 13B of the lead frame 10B are disposed. After the bonding pads 21B of the semiconductor chip 20B have been connected to the bonding pads 13B of the lead frame 10B by wires 14B, the semiconductor chip 20B and the wires 14B are resin-sealed with a resin member 15B.
FIGS. 16A, 16B and 16C are schematic structural views showing a semiconductor device of a conventional multi-chip package configuration, with FIG. 16A being a plan view seen from an upper surface, FIG. 16B being a bottom view seen from an undersurface, and FIG. 16C being a longitudinal sectional view. Elements in common with elements of FIGS. 15A and 15B are designated by common reference numerals.
In this semiconductor device, semiconductor chips 20B and 20C that have the same function are mounted on an upper surface and on an undersurface of the die pad 11B of the lead frame 10B of FIGS. 15A and 15B for the purpose of, for example, doubling memory capacity.
As shown in FIG. 16A, the lead frame 10B includes the die pad 11B, which is rectangular in plan view, and plural leads 12B that are horizontally disposed at a predetermined distance away from left and right edges of the die pad 11B. The leads 12B include inner lead portions disposed with bonding pads 13B (left-side bonding pads 13B-11, 13B-12, . . . , and right-side bonding pads 13B-21, 13B-22, . . . ) and outer lead portions that are horizontally pulled out.
Bonding pads 21B (left-side bonding pads 21B-11, 21B-12, . . . , and right-side bonding pads 21B-21, 21B-22, . . . ) are disposed near left and right edges of an upper surface of the semiconductor chip 20B on the upper side of the die pad 11B in correspondence to the bonding pads 13B-11, 13B-12, . . . , 13B-21, 13B-22, . . . of the lead frame 10B. The left-side bonding pads 21B-11, 21B-12, . . . are connected to the left-side bonding pads 13B-11, 13B-12, . . . of the lead frame 10B via plural wires 14B. The right-side bonding pads 21B-21, 21B-22, . . . are connected to the right-side bonding pads 13B-21, 13B-22, . . . of the lead frame 10B.
When a semiconductor chip having the same structure (i.e., when the disposition of the bonding pads thereof is the same) as that of the semiconductor chip 20B on the upper surface of the die pad 11B is used as the semiconductor chip 20C on the undersurface of the die pad 11B, wires 14C cross and short because the disposition of the bonding pads is reversed right/left or up/down when seen from the upper side of the die pad 11B. In order to prevent this, a mirror chip, in which the disposition of the bonding pads and inner element circuitry are inverted (i.e., so that top and bottom face, or mirror, each other) to become rotationally symmetrical with respect to the semiconductor chip 20B on the upper surface of the lead frame 10B, is used for the semiconductor chip 20C on the undersurface of the lead frame 10B.
As shown in FIG. 16B, the mirror chip-structure semiconductor chip 20C is disposed with bonding pads 21C (right-side bonding pads 21C-11, 21C-12, . . . , and left-side bonding pads 21C-21, 21C-22, . . . ) near right and left edges thereof (since the semiconductor chip 20C is being viewed from its undersurface, left/right are opposite) in correspondence to the bonding pads 13B-11, 13B-12, . . . , 13B-21, 13B-22, . . . of the lead frame 10B. The right-side bonding pads 21C-11, 21C-12, . . . are connected to the left-side (when seen from the upper surface of the lead frame 10B) bonding pads 13B-11, 13B-12, . . . by the plural wires 14C. The left-side bonding pads 21C-21, 21C-22, . . . are connected to the right-side (when seen from the upper surface of the lead frame 10B) bonding pads 13B-21, 13B-22, . . .
The semiconductor chips 20B and 20C and the wires 14B and 14C are resin-sealed with the resin member 15B.
However, there have been the following problems (1) and (2) in the aforementioned conventional semiconductor devices and their methods of production.
(1) Problems in the Conventional Devices of FIGS. 14A to 15B
When the semiconductor chip 20A of FIGS. 14A and 14B is mounted in the package of FIGS. 15A and 15B, the positions at which the bonding pads of each are disposed become different and a short is generated due to the wires crossing. Thus, the bonding pads cannot be connected by the wires 14A. For this reason, it is necessary to newly create the semiconductor chip 20B of FIGS. 15A and 15B, which has the same function as that of the semiconductor chip 20A and in which the positions of the bonding pads are moved.
Thus, in the semiconductor devices of FIGS. 14A and 14B and FIGS. 15A and 15B, it is necessary to design and create a semiconductor chip for a certain package each time the configuration of that package changes. Moreover, enormous expenses and time to develop the created semiconductor chip become necessary because it is necessary to test the quality of the created semiconductor chip by blocking and the like (to verify operation). The size of the chip also becomes larger due to disposing the bonding pads of the semiconductor chip 20B to match the package of FIGS. 15A and 15B, or else it becomes necessary to maintain stocks relating to each of the semiconductor chips.
In order to eliminate such drawbacks, it is conceivable to dispose, as disclosed in Document 1, a metal wiring film on the semiconductor chip 20A of FIGS. 14A and 14B for converting the pad positions, and connect the bonding pads 21A of the semiconductor chip 20A of FIGS. 14A and 14B to the bonding pads 13B of the lead frame 10B of FIGS. 15A and 15B with wires through the metal wiring film. Alternatively, it is also conceivable to fix, as disclosed in Document 2, a signal position-converter having a wiring pattern, mount the semiconductor chip 20A of FIGS. 14A and 14B thereon, and connect the bonding pads 21A of the semiconductor chip 20A of FIGS. 14A and 14B to the bonding pads 13B of the lead frame 10A of FIGS. 15 and 15B with wires through the signal position-converter.
However, because a wiring structure for relay is not established in structures or methods in which the metal wiring film of Document 1 or the signal position-converter of Document 2 is disposed and bonding pads are wire-bonded, the wiring structure for relay is changed together with changes in the positions of the bonding pads of the semiconductor chip and the bonding pads of the lead frame. Therefore, there has been the potential for new peripheral devices to become necessary and for costs to increase exorbitantly when, for example, blocking or the like is conducted to test operation.
(2) Problems in the Conventional Device of FIGS. 16A to 16C
Because it is necessary to prepare two kinds of semiconductor chips (i.e., the upper-side semiconductor chip 20B and the under-side semiconductor chip 20C, which is a mirror chip of the semiconductor chip 20B), it is necessary to design and create two kinds of semiconductor chips for a certain package each time the configuration of that packages changes. Moreover, because it is necessary to test the quality of the created two kinds of semiconductor chips by blocking and the like (to verify operation), costs increase and the sizes of the chips become larger, or else it becomes necessary to maintain stocks relating to each of the semiconductor chips.
In order to eliminate such drawbacks, it is conceivable to use the metal wiring film for converting pad positions as disclosed in Document 1 or to use the signal position-converter having a wiring pattern as disclosed in Document 2. However, similar to (1) above, there has been the potential for new peripheral devices to become necessary and for costs to increase exorbitantly when, for example, blocking or the like is conducted to test operation.
It is an object of the present invention to provide a semiconductor device and a method of producing a semiconductor device that can eliminate the aforementioned problems in the prior art and in which disposal and replacement of bonding pads can be conducted easily and accurately.
In order to achieve the aforementioned object, a first aspect of the invention provides a semiconductor device comprising: a substrate including a first surface and a second surface; first bonding pads disposed outside the substrate near a periphery of the substrate; a semiconductor chip including an upper surface disposed with second bonding pads and an undersurface mounted on the substrate first surface; at least one relay chip including an upper surface disposed with third bonding pads, a first wiring pattern formed of wiring for connecting corresponding pad pairs of the third bonding pads, and an undersurface mounted on the upper surface of the semiconductor chip; and lead wires for electrically connecting the first bonding pads and the second bonding pads of the semiconductor chip, wherein one first bonding pad and one third bonding pad corresponding to the one first bonding pad are electrically connected via one lead wire, and another third bonding pad connected via one wiring to the one third bonding pad and a second bonding pad corresponding to the another third bonding pad are electrically connected via another lead wire.
Because the relay chip is superimposed on the semiconductor chip and the disposition of the pads is converted using the relay chip so that the pads can be connected to the first bonding pads, it is not necessary to alter the disposition of the bonding pads of the semiconductor chip and it is possible to wire-bond the pads to the first bonding pads of various modes of disposition. Moreover, because it is possible to structure the relay chip with only the bonding pads and the wiring pattern, it is possible to reduce developmental expenses or expenses necessary to redesign and test the operation of the semiconductor chip in comparison with the case in which a semiconductor chip is created in which the disposition of the pads has been altered. Additionally, because the relay chip is fixed to fit within an outer periphery of the semiconductor chip, it is possible to strongly fix the relay chip at a predetermined position, and it is possible to easily and accurately mount and wire-bond the relay chip without the relay chip deviating from a predetermined mounting position due to force applied thereto when the relay chip is mounted and wire-bonded. Also, the wiring pattern of the relay chip can be variously configured to correspond to the direction in which the disposition of the pads is converted. When drawbacks arise in this case, such a short occurring between wires when the wires are complicated, the wiring pattern can be configured to a multi-layer interconnection structure.
When plural relay chips are used, the lengths of the wires can be shortened and reliability can be improved by disposing the relay chips near the periphery of the semiconductor chip. Moreover, because the size of each relay chip can be reduced, it is possible to reduce costs by reducing breakage and raising chip yield.
When plural relay chips are given the same structure, it is possible to reduce costs by reducing the kinds of chips used.
The semiconductor device according to the first aspect further comprises: a second semiconductor chip including an upper surface disposed with bonding pads and an undersurface mounted on the substrate second surface; and lead wires for electrically connecting the bonding wires with the first bonding pads.
Because the direction of the pads on one semiconductor chip is converted to the direction in which the pads are disposed on the other semiconductor chip using the first and second semiconductor chips that have the same structure, it is possible to easily produce a semiconductor device having a multi-chip package configuration without using the mirror chip that was conventionally necessary, and a reduction in cost due to the elimination of the mirror chip can be expected.
A second aspect of the invention provides a semiconductor device comprising: a substrate; first bonding pads disposed outside the substrate near a periphery of the substrate; plural semiconductor chips, each semiconductor chip including an upper surface disposed with second bonding pads and an undersurface mounted on a surface of the substrate; a relay chip including an upper surface disposed with third bonding pads, a wiring pattern formed of wiring for connecting corresponding pad pairs of the third bonding pads, and an undersurface mounted on the upper surfaces of the semiconductor chips; and lead wires for electrically connecting the first bonding pads and the second bonding pads of the semiconductor chip, wherein one first bonding pad and one third bonding pad corresponding to the one first bonding pad are electrically connected via one lead wire, and another third bonding pad connected via one wiring to the one third bonding pad and a second bonding pad corresponding to the another third bonding pad are electrically connected via another lead wire.
Because the relay chip is superimposed on the plural semiconductor chips and the disposition of the pads is converted by the relay chip, a multi-chip semiconductor device can be produced without constraints on the disposition of the pads. Moreover, because it is possible to structure the relay chip with only the bonding pads and the wiring pattern, it is possible to reduce developmental expenses or expenses necessary to redesign and test the operation of the semiconductor chip in comparison with the case in which a semiconductor chip is created in which the disposition of the pads has been altered. Additionally, because the relay chip is superimposed on the semiconductor chips, increases in area in the horizontal direction can be suppressed and the semiconductor device can be made compact. When the relay chip is fixed to fit within an outer periphery of an area formed by the semiconductor chips, it is possible to easily and accurately mount and wire-bond the relay chip.
In accordance with a third aspect of the invention, there is provided a method of producing a semiconductor, the method comprising the steps of: providing a substrate and first bonding pads disposed outside the substrate near a periphery of the substrate, and mounting a semiconductor chip that includes second bonding pads on the substrate; mounting at least one relay chip on the semiconductor chip, the at least one relay chip including third bonding pads and a wiring pattern formed of wiring for connecting corresponding pad pairs of the third bonding pads; electrically connecting the first bonding pads to the second bonding pads of the semiconductor chip using lead wires, so that one first bonding pad and one third bonding pad corresponding to the one first bonding pad are electrically connected via one lead wire, and another third bonding pad connected via one wiring to the one third bonding pad and a second bonding pad corresponding to the another third bonding pad are electrically connected via another lead wire; and sealing the substrate, the semiconductor chip, the at least one relay chip, and the lead wires with a resin member. Preferably, the wiring pattern includes a multi-layer interconnection structure comprising interlayer insulating films and conductive films that are alternatingly disposed. Further, preferably, the substrate is a die pad of a lead frame.